1. Field of the Invention
The present invention relates to a field of processor design, and, more specifically, to an apparatus for and a method of sharing cache resources between different engines.
2. Discussion of Related Art
Computing power of processors is increasing much faster than bandwidth available from main memory. As a result, increasingly large and complex caches need to be designed to support and feed compute-intensive engines in the processors.
However, allocating more transistors to cache results in the cache occupying a larger portion of die area. Furthermore, available cache resources, no matter how large, become increasingly difficult to allocate.
In particular, partitioning of the cache resources among various compute engines to obtain optimal performance for different workloads becomes very difficult to achieve effectively and efficiently.